/* --------------------------------------------------------------------------
 *	Cyrix 5520 companion chip definitions
 * --------------------------------------------------------------------------
 *
 *	Copyright (C) 1997		Emmanuel Marty
 *	Copyright (C) 1997		Cyrix Corporation
 *	Copyright (C) 1997		The GGI project
 *
 *	This program is free software; you can redistribute it and/or modify
 *	it under the terms of the GNU General Public License as published by
 *	the Free Software Foundation; either version 2, or (at your option)
 *	any later version.
 * 
 *	You should have received a copy of the GNU General Public License
 *	along with this program; see the file COPYING.  If not, write to
 *	the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 * --------------------------------------------------------------------------
 *
 *	This code was derived from the following sources of information :
 *
 *	Cyrix MediaGX confidential databooks
 *	Cyrix MediaGX gxvideo.c example sourcecode
 *	Help and code from Sengan Baring-Gould of Cyrix Corporation
 *
 *	Many thanks to the Cyrix Corporation for providing me with
 *	documentation and official support about the GX chipset family.
 *
 * --------------------------------------------------------------------------
 *
 *	MAINTAINER	Emmanuel_Marty
 *
 *	$Log: cx5520.h,v $
 *	Revision 1.1  1998/07/07 08:16:42  taylorj
 *	*** empty log message ***
 *	
 *	Revision 1.2  1998/01/29 09:12:55  emarty
 *	working on 5520 support
 *	
 *	Revision 1.1  1997/12/20 12:57:58  emarty
 *	major: initial checkin
 *	
 *
 */

#ifndef _CYRIX_CX5520_H
#define _CYRIX_CX5520_H
 
#define CX5520_CFG_VIDEO_BASE		0x1C	/* video base register */

/*	VIDEO REGISTER OFFSETS			*/

#define CX5520_VIDEO_CONFIG		0x0000	/* video configuration */
#define CX5520_DISPLAY_CONFIG		0x0004	/* display configuration */
#define CX5520_VIDEO_X_POS		0x0008	/* video X position */
#define CX5520_VIDEO_Y_POS		0x000C	/* video Y position */
#define CX5520_VIDEO_SCALE		0x0010	/* video scale */
#define CX5520_VIDEO_COLOR_KEY		0x0014	/* video color key */
#define CX5520_VIDEO_COLOR_MASK   	0x0018	/* video color mask */
#define CX5520_PALETTE_ADDRESS		0x001C	/* palette address */
#define CX5520_PALETTE_DATA		0x0020	/* palette data	*/

/*	DISPLAY CONFIGURATION BIT DEFINITIONS	*/

#define CX5520_DCFG_DIS_EN		0x00000001
#define CX5520_DCFG_HSYNC_EN		0x00000002
#define CX5520_DCFG_VSYNC_EN		0x00000004
#define CX5520_DCFG_DAC_BL_EN		0x00000008
#define CX5520_DCFG_DAC_PWDNX		0x00000020
#define CX5520_DCFG_FP_PWR_EN		0x00000040
#define CX5520_DCFG_FP_DATA_EN		0x00000080
#define CX5520_DCFG_CRT_HSYNC_POL 	0x00000100
#define CX5520_DCFG_CRT_VSYNC_POL 	0x00000200
#define CX5520_DCFG_FP_HSYNC_POL  	0x00000400
#define CX5520_DCFG_FP_VSYNC_POL  	0x00000800
#define CX5520_DCFG_XGA_FP		0x00001000
#define CX5520_DCFG_FP_DITH_EN		0x00002000
#define CX5520_DCFG_CRT_SYNC_SKW_MASK	0x0001C000
#define CX5520_DCFG_CRT_SYNC_SKW_POS	14
#define CX5520_DCFG_PWR_SEQ_DLY_MASK	0x000E0000
#define CX5520_DCFG_PWR_SEQ_DLY_POS	17
#define CX5520_DCFG_PWR_SEQ_DLY_MASK	0x000E0000
#define CX5520_DCFG_VG_CK		0x00100000
#define CX5520_DCFG_GV_PAL_BYP		0x00200000
#define CX5520_DCFG_DDC_SCL		0x00400000
#define CX5520_DCFG_DDC_SDA		0x00800000
#define CX5520_DCFG_DDC_OE		0x01000000

/*	CLOCK REGISTER OFFSETS			*/

#define CX5520_AUDIOCLK_CONTROL1	0x0E00	/* Audio configuration 1 */
#define CX5520_AUDIOCLK_CONTROL2	0x0E04	/* Audio configuration 2 */
#define CX5520_CLK_32K_CONTROL1		0x0E08	/* CLK_32K PLL control 1 */
#define CX5520_CLK_32K_CONTROL2		0x0E0C	/* CLK_32K PLL control 2 */
#define CX5520_SCLK_CONTROL		0x0E10	/* S clock PLL control */
#define CX5520_DCLK_CONTROL		0x0E14	/* Dot clock PLL control */
#define CX5520_CLK_STATUS0		0x0E18	/* Status 0 register */
#define CX5520_CLK_STATUS1		0x0E1C	/* Status 1 register */
#define CX5520_USBCLK_CONTROL		0x0E24	/* USB PLL control */

#endif	/* _CYRIX_CX5520_H */